Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor
- authored by
- Johannes Kneip, Martin Ohmacht, Jens Peter Wittenburg, Peter Pirsch
- Abstract
The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
- Organisation(s)
-
Laboratorium f. Informationstechnologie
- Type
- Conference article
- Journal
- Proceedings - IEEE International Symposium on Circuits and Systems
- Volume
- 4
- Pages
- 316-319
- No. of pages
- 4
- ISSN
- 0271-4310
- Publication date
- 1996
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Electrical and Electronic Engineering
