Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor

verfasst von

Johannes Kneip, Martin Ohmacht, Jens Peter Wittenburg, Peter Pirsch

Abstract

The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Band

4

Seiten

316-319

Anzahl der Seiten

4

ISSN

0271-4310

Publikationsdatum

1996

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik