An advanced programmable 2D-convolution chip for real time image processing

authored by

V. Hecht, K. Ronner, P. Pirsch

Abstract

An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations.

Organisation(s)

Laboratorium f. Informationstechnologie

Type

Conference article

Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

4

Pages

1897-1900

No. of pages

4

ISSN

0271-4310

Publication date

1991

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering