An advanced programmable 2D-convolution chip for real time image processing

verfasst von

V. Hecht, K. Ronner, P. Pirsch

Abstract

An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Band

4

Seiten

1897-1900

Anzahl der Seiten

4

ISSN

0271-4310

Publikationsdatum

1991

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik