Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets

authored by

Holger Blume, Thorsten Von Sydow, Tobias G. Noll

Abstract

Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze onchip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modern heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.

External Organisation(s)

RWTH Aachen University

Type

Conference contribution

Pages

484-493

No. of pages

10

Publication date

2004

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Theoretical Computer Science, General Computer Science

Electronic version(s)

https://doi.org/10.1007/978-3-540-27776-7_50 (Access: Closed)