Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique
- authored by
- Niklas Deneke, Bernhard Wicht
- Abstract
Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.
- Organisation(s)
-
Institute of Microelectronic Systems
- Type
- Conference contribution
- Pages
- 2409-2414
- No. of pages
- 6
- Publication date
- 2024
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1109/APEC48139.2024.10509192 (Access:
Closed)