Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

verfasst von

Peter Pirsch, Johannes Kneip, Karsten Roenner

Abstract

For the design of a highly parallel programmable videosignal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Band

1

Seiten

562-565

Anzahl der Seiten

4

ISSN

0271-4310

Publikationsdatum

1995

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik