High Temperature In-Order RISC-V Processor with Heterogeneous Pipeline and Out-of-Order Write-Back Mechanism

verfasst von: Malte Hawich, Holger Christoph Blume, Jan Szücs
Abstract: Modern deep drilling operations depend on a complex network of sensors, actuators, and controllers installed
at the drill string’s bottom end. These electronic components
must withstand extreme conditions, including temperatures up
to 175 °C and pressures reaching 200 MPa. Due to the lack of
fast communication to the surface, autonomous in situ digital
signal processing is essential. To address these challenges, a highperformance RISC-V processor has been developed, capable of
reliable operation in such harsh environments. The XT018 180-
nanometer Silicon-on-Insulator (SOI) process from XFAB was
selected for its advanced capabilities, ensuring the production of
robust electronic circuits suited for these extreme conditions. [1].
Conventional RISC-V architectures typically employ a five-stage
pipeline design, which constrains the execution phase to a single
stage and limits digital signal processing (DSP) capabilities. To
address this, the custom RISC-V processor features a heterogeneous execution pipeline, with unit delays ranging from one
cycle to 29 cycles [2]. This instruction-dependent pipeline length
enables the RV32IMCF processor to achieve clock speeds of
up to 180 MHz for 175 °C with is up to 4 times higher than
typical processors in similar application specific integrated circuit
(ASIC) technologies [3], [4]. To further enhance performance,
this new contribution introduces out-of-order writebacks and a
split writeback mechanism that operates independently from the
issue stage. These innovations effectively manage Write After
Write (WAW) hazards and general hazard detection, maintaining
reliable operation. The design ensures that multiple instructions
executed by the same unit remain in order. Synchronization of
the asymmetric processor execution stages is managed through
handshakes, which, while adding control logic to each execution
unit, relieve the controller of significant workload. Compared
to an RV32IMFC processor limited to single-cycle execution
stages, this advanced design achieves up to 18 times higher clock
frequencies. Additionally, the out-of-order writebacks and split
independent writeback mechanism deliver at least a 5% performance boost over previous designs, with potential improvements
of up to 50% in benchmarks that fully exploit these capabilities,
showcasing substantial enhancements in processing efficiency and
throughput.
Organisationseinheit(en): Fachgebiet Architekturen und Systeme
Typ: Aufsatz in Konferenzband
Seiten: 1-4
Anzahl der Seiten: 4
Publikationsdatum: 24.09.2024
Publikationsstatus: Veröffentlicht
Peer-reviewed: Ja
ASJC Scopus Sachgebiete: Computernetzwerke und -kommunikation, Angewandte Informatik, Geophysik, Elektrotechnik und Elektronik, Instrumentierung, Strahlung
Elektronische Version(en): https://doi.org/10.23919/IEEECONF64570.2024.10738940 (Zugang: Geschlossen)

BibTeX

@inproceedings{e1b133bd13ba4fb5b35adfa8a8c9dfc6,
title = "High Temperature In-Order RISC-V Processor with Heterogeneous Pipeline and Out-of-Order Write-Back Mechanism",
abstract = "Modern deep drilling operations depend on a complex network of sensors, actuators, and controllers installedat the drill string{\textquoteright}s bottom end. These electronic componentsmust withstand extreme conditions, including temperatures upto 175 °C and pressures reaching 200 MPa. Due to the lack offast communication to the surface, autonomous in situ digitalsignal processing is essential. To address these challenges, a highperformance RISC-V processor has been developed, capable ofreliable operation in such harsh environments. The XT018 180-nanometer Silicon-on-Insulator (SOI) process from XFAB wasselected for its advanced capabilities, ensuring the production ofrobust electronic circuits suited for these extreme conditions. [1].Conventional RISC-V architectures typically employ a five-stagepipeline design, which constrains the execution phase to a singlestage and limits digital signal processing (DSP) capabilities. Toaddress this, the custom RISC-V processor features a heterogeneous execution pipeline, with unit delays ranging from onecycle to 29 cycles [2]. This instruction-dependent pipeline lengthenables the RV32IMCF processor to achieve clock speeds ofup to 180 MHz for 175 °C with is up to 4 times higher thantypical processors in similar application specific integrated circuit(ASIC) technologies [3], [4]. To further enhance performance,this new contribution introduces out-of-order writebacks and asplit writeback mechanism that operates independently from theissue stage. These innovations effectively manage Write AfterWrite (WAW) hazards and general hazard detection, maintainingreliable operation. The design ensures that multiple instructionsexecuted by the same unit remain in order. Synchronization ofthe asymmetric processor execution stages is managed throughhandshakes, which, while adding control logic to each executionunit, relieve the controller of significant workload. Comparedto an RV32IMFC processor limited to single-cycle executionstages, this advanced design achieves up to 18 times higher clockfrequencies. Additionally, the out-of-order writebacks and splitindependent writeback mechanism deliver at least a 5% performance boost over previous designs, with potential improvementsof up to 50% in benchmarks that fully exploit these capabilities,showcasing substantial enhancements in processing efficiency andthroughput.",
keywords = "Out of order, Application specific integrated circuits, Time-frequency analysis, Pipelines, Digital signal processing, Benchmark testing, Throughput, Hazards, Integrated circuit reliability, Clocks, RISC-V, Controller, High Performance, ASIC, Hardware Design, Out-of-order, In-order, Harsh Environment",
author = "Malte Hawich and Blume, {Holger Christoph} and Jan Sz{\"u}cs",
note = "Publisher Copyright: {\textcopyright} 2024 Deutscher Landesausschuss in der Bundesrepublik Deutschland e.V.; 2024 Kleinheubach Conference ; Conference date: 24-09-2024 Through 26-09-2024",
year = "2024",
month = sep,
day = "24",
doi = "10.23919/IEEECONF64570.2024.10738940",
language = "English",
isbn = "979-8-3315-4177-4",
pages = "1--4",
booktitle = "2024 Kleinheubach Conference",
url = "https://kh2024.de/",
}