Single-chip highly parallel architecture for image processing applications

verfasst von: Johannes Kneip, Karsten Roenner, Peter Pirsch
Abstract: For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.
Organisationseinheit(en): Laboratorium f. Informationstechnologie
Typ: Aufsatz in Konferenzband
Seiten: 1753-1764
Anzahl der Seiten: 12
Publikationsdatum: 1994
Publikationsstatus: Veröffentlicht
Peer-reviewed: Ja
ASJC Scopus Sachgebiete: Elektronische, optische und magnetische Materialien, Physik der kondensierten Materie, Angewandte Informatik, Angewandte Mathematik, Elektrotechnik und Elektronik

BibTeX

@inproceedings{7dd3e069aad54aa2830a83be7d7a73b9,
title = "Single-chip highly parallel architecture for image processing applications",
abstract = "For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.",
author = "Johannes Kneip and Karsten Roenner and Peter Pirsch",
year = "1994",
language = "English",
isbn = "081941638X",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
publisher = "Society of Photo-Optical Instrumentation Engineers",
number = "p 3",
pages = "1753--1764",
booktitle = "Proceedings of SPIE",
edition = "p 3",
note = "Visual Communications and Image Processing '94 ; Conference date: 25-09-1994 Through 29-09-1994",
}