HiPAR-DSP

A parallel VLIW RISC processor for real time image processing applications

verfasst von: J. P. Wittenburg, M. Ohmacht, J. Kneip, W. Hinrichs, P. Pirsch
Abstract: Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm ² , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.
Organisationseinheit(en): Laboratorium f. Informationstechnologie
Typ: Aufsatz in Konferenzband
Seiten: 155-162
Anzahl der Seiten: 8
Publikationsdatum: 1997
Publikationsstatus: Veröffentlicht
Peer-reviewed: Ja
ASJC Scopus Sachgebiete: Computernetzwerke und -kommunikation, Hardware und Architektur, Signalverarbeitung
Elektronische Version(en): https://doi.org/10.1109/ICAPP.1997.651487 (Zugang: Geschlossen)

BibTeX

@inproceedings{6c092e02fd364cfebc1bd0ec47809db9,
title = "HiPAR-DSP: A parallel VLIW RISC processor for real time image processing applications",
abstract = " Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm 2 , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.",
author = "Wittenburg, {J. P.} and M. Ohmacht and J. Kneip and W. Hinrichs and P. Pirsch",
year = "1997",
doi = "10.1109/ICAPP.1997.651487",
language = "English",
series = "1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "155--162",
editor = "Wanlei Zhou and Andrzej Goscinski and Michael Hobbs",
booktitle = "1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997",
address = "United States",
note = "3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997 ; Conference date: 10-12-1997 Through 12-12-1997",
}