Architecture of a multiprocessor system with embedded DRAM for large area integration

verfasst von

Klaus Herrmann, Joerg Hilgenstock, Peter Pirsch

Abstract

The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Seiten

274-281

Anzahl der Seiten

8

ISSN

1063-2204

Publikationsdatum

1997

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Hardware und Architektur, Elektrotechnik und Elektronik, Physik der kondensierten Materie