A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs

verfasst von

Jesko Flemming, Bernhard Wicht, Pascal Witte

Abstract

This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

Hochschule Hannover (HsH)

Typ

Aufsatz in Konferenzband

Anzahl der Seiten

5

Publikationsdatum

2024

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1109/ISCAS58744.2024.10557987 (Zugang: Geschlossen)