Parallel, Hardware-Supported Interrupt Handling in an Event-Triggered Real-Time Operating System

verfasst von: Fabian Scheler, Wanja Hofer, Benjamin Oechslein, Rudi Pfister, Wolfgang Schröder-Preikschat, Daniel Lohmann
Abstract: A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks that are implemented as threads. This problem is termed rate-monotonic priority inversion, and current software-based solutions are restricted in terms of more sophisticated scheduler features as demanded for instance by the AUTOSAR embedded-operating-system specification. We propose a hardware-based approach that makes use of a coprocessor to eliminate the potential priority inversion. By evaluating a prototypical implementation, we show that our approach both overcomes the restrictions of software approaches and introduces only a slight processing overhead in exchange for increased predictability.
Externe Organisation(en): Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU Erlangen-Nürnberg)
Typ: Aufsatz in Konferenzband
Seiten: 167-174
Anzahl der Seiten: 8
Publikationsdatum: 01.2009
Publikationsstatus: Veröffentlicht
Peer-reviewed: Ja
ASJC Scopus Sachgebiete: Hardware und Architektur, Software, Elektrotechnik und Elektronik
Elektronische Version(en): https://doi.org/10.1145/1629395.1629419 (Zugang: Unbekannt)

BibTeX

@inproceedings{97aa8048ea10498eaf6e50be066f5d28,
title = "Parallel, Hardware-Supported Interrupt Handling in an Event-Triggered Real-Time Operating System",
abstract = "A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks that are implemented as threads. This problem is termed rate-monotonic priority inversion, and current software-based solutions are restricted in terms of more sophisticated scheduler features as demanded for instance by the AUTOSAR embedded-operating-system specification. We propose a hardware-based approach that makes use of a coprocessor to eliminate the potential priority inversion. By evaluating a prototypical implementation, we show that our approach both overcomes the restrictions of software approaches and introduces only a slight processing overhead in exchange for increased predictability.",
keywords = "CiAO, Interrupt handling, Priority-driven, Rate-monotonic priority inversion, Real-time systems, TriCore",
author = "Fabian Scheler and Wanja Hofer and Benjamin Oechslein and Rudi Pfister and Wolfgang Schr{\"o}der-Preikschat and Daniel Lohmann",
year = "2009",
month = jan,
doi = "10.1145/1629395.1629419",
language = "English",
isbn = "9781605586267",
pages = "167--174",
booktitle = "CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems",
note = "Embedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09 ; Conference date: 11-10-2009 Through 16-10-2009",
}