Data path array with shared memory as core of a high performance DSP

verfasst von

J. Kneip, K. Roenner, P. Pirsch

Abstract

A data path array design combining shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerful core of a high-performance digital signal processor (DSP) on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 × 4 array, the processor will perform a 1024 samples complex FFT within 3 μs including data I/O. The Hough transform of a 512 × 512 pel image with 30% black pels is performed within 66 ms, assuming 7 bit quantization for the angle and 11 bit quantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Proceedings of the International Conference on Application Specific Array Processors

Seiten

271-282

Anzahl der Seiten

12

ISSN

1063-6862

Publikationsdatum

1994

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Hardware und Architektur, Computernetzwerke und -kommunikation