Hierarchical multiprocessor architecture for video coding applications

verfasst von

P. Pirsch, W. Gehrke, R. Hoffer

Abstract

A hierarchical multiprocessor architecture for real time video coding applications is presented. Due to the properties of actual video coding standards two strategies can be utilized for parallelization, data distribution and task distribution. To exploit the advantages of both approaches a combination of the named strategies is used in the proposed hierarchical multiprocessor architecture. For optimization of the architecture an efficiency measure is introduced which considers processing time, silicon area as well as the yield of the semiconductor process. Results are given for an implementation example.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Aufsatz in Konferenzband

Seiten

1750-1753

Anzahl der Seiten

4

Publikationsdatum

1993

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik